This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-162671, filed May 31, 2000; No. 2000-169002, filed Jun. 6, 2000; and No. 2001-128909, filed Apr. 26, 2001, the entire contents of all of which are incorporated herein by reference.
The present invention relates to a shift register and an electronic apparatus such as a display unit or an imaging apparatus, using this shift register as a driver.
In an active matrix type liquid crystal display such as a TFT liquid crystal display, each one line of display pixels arranged in the matrix form is selected, and display data is written in a pixel capacitance of the selected pixels, thereby obtaining desired display.
In the TFT liquid crystal display, there are used a gate driver for serially outputting a gate signal for pixel selection to a gate of the TFT functioning as a pixel switching device, and a drain driver for outputting a drain signal which serves as image data during a gate selection period in parallel. Since the drain driver which outputs usual moving image data must be constituted by multiple complex transistors and driven at a high speed, there is adopted a driver consisting of monocrystal silicon or polysilicon which can reduce the size of the transistors and has the high mobility.
On the other hand, since the structure of the gate driver is not very complicated as the drain electrode and the gate driver has a low driving frequency, it can be theoretically driven by a driver consisting of amorphous silicon TFTs but it has not been put into practical use.
Among the gate drivers constituted by multiple amorphous silicon TFTs, there are drivers having a threshold value characteristic of each TFT being shifted with a lapse of time, or those disadvantageously causing an erroneous operation in the high-temperature environment.
It is an object of the present invention to provide a shift register which can obtain a correct circuit operation even at a high temperature and obtain a stable operation in a long period of time.
According to a first aspect of the present invention there is provided a shift register,
each stage of the shift register comprising:
a first transistor which has a first control terminal, is turned on by a signal on a predetermined level supplied from one stage to the first control terminal, and outputs the signal on a predetermined level from one end of a first electric current path to the other end of the first electric current path;
a second transistor which has a second control terminal, is turned on in accordance with a voltage applied to a wiring between the second control terminal and the other end of the first electric current path of the first transistor, and outputs a first or second signal supplied from outside to one end of a second electric current path as an output signal from the other end of the second electric current path;
a load for outputting a power supply voltage supplied from outside;
a third transistor which has a third control terminal, is turned on in accordance with a voltage applied to a wiring between the third control terminal and the other end of the first electric current path of the first transistor, and outputs the power supply voltage supplied from the outside through the load from one end of a third electric current path to the other end of the third electric current path so that the power supply voltage outputted from the load is displaced to a voltage on a predetermined level; and
a fourth transistor which has a fourth control terminal, is turned on in accordance with a voltage applied to a wiring between the fourth control terminal and the load, and outputs a reference voltage to one end of a fourth electric current path from the other end of the fourth electric current path, one end of the fourth electric current path being connected to the other end of the second electric current path of the second transistor,
a value (a channel-width/a channel-length of the fourth transistor) being equal to or larger than another value (a channel width of the second transistor/a channel length of the second transistor).
According to a second aspect of the present invention, there is provided a shift register
each stage of the shift register comprising:
a first transistor which has a first control terminal, is turned on by a signal on a predetermined level supplied from one stage to the first control terminal, and outputs the signal on a predetermined level from one end of a first electric current path to the other end of the first electric current path;
a second transistor which has a second control terminal, is turned on in accordance with a voltage applied to a wiring between the second control terminal and the other end of the first electric current path of the first transistor, and outputs a first or second signal supplied from outside to one end of a second electric current path as an output signal from the other end of the second electric current path;
a third transistor which has a third control terminal and outputs a power supply voltage from one end of a third electric current path to the other end of the third electric current path;
a fourth transistor which has a fourth control terminal, is turned on in accordance with a voltage applied to a wiring between the fourth control terminal and the other end of the first electric current path of the first transistor, and outputs from one end of a fourth electric current to the other end of the fourth electric current path the power supply voltage supplied from the third transistor so that the power supply voltage outputted from the third transistor is displaced to a voltage on a predetermined level;
a fifth transistor which has a fifth control terminal, is turned on in accordance with a voltage applied to a wiring between the fifth control terminal and the third transistor, and outputs a reference voltage to one end of a fifth electric current path from the other end of the fifth electric current path, one end of the fifth electric current path being connected to the other end of the second electric current path of the second transistor; and
a sixth transistor which has a sixth control terminal and resets a voltage applied to the wiring between the second control terminal of the second transistor and the first electric current path of the first transistor when turned on by turning on the sixth control terminal by an output signal of the other stage,
a value (a channel-width/a channel-length of the fifth transistor) being larger than another value (a channel-width/a channel-length of the first transistor).
According to a third aspect of the present invention, there is provided a shift register,
each stage of the shift register comprising:
a first transistor having a control terminal to which an output signal of a stage on one side is supplied and one end of an electric current path to which a first voltage signal is supplied;
a second transistor having a control terminal to which an output signal of a stage on the other side is supplied and one end of an electric current path to which a second voltage signal is supplied; and
a third transistor which has a control terminal being connected to the other end of each electric current path of the first and second transistors, is turned on or off by the first or second voltage signal supplied to a wiring between the control terminal and the other end of each electric current path through the first or second transistor, and outputs from the other end of the electric current path a first or second clock signal supplied to one end of the electric current path as an output signal of that stage when turned on,
at least one of the first and second transistor being constituted so as to be capable of discharging electric charge accumulated in the wiring by an output signal of the stage on one side or the other side supplied to the control terminal.
According to a forth aspect of the present invention, there is provided an electronic apparatus comprising:
(A) a shift register including on each stage:
a first transistor which has a first control terminal, is turned on by a signal on a predetermined level supplied from one stage to the first control terminal, and outputs the signal on a predetermined level from one end of a first electric current path to the other end of the first electric current path;
a second transistor which has a second control terminal, is turned on in accordance with a voltage applied to a wiring between the second control terminal and the other end of the first electric current path of the first transistor, and outputs a first or second signal supplied from outside to one end of a second electric current path as an output signal from the other end of the second electric current path;
a third transistor which has a third control terminal and outputs a power supply voltage from one end of a third electric current path to the other end of the third electric current path;
a fourth transistor which has a fourth control terminal, is turned on in accordance with a voltage applied to a wiring between the fourth control terminal and the other end of the first electric current path of the first transistor, and outputs from one end of a fourth electric current to the other end of the fourth electric current path the power supply voltage supplied from the third transistor so that the power supply voltage outputted from the third transistor is displaced to a voltage on a predetermined level;
a fifth transistor which has a fifth control terminal, is turned on in accordance with a voltage applied to a wiring between the fifth control terminal and the third transistor, and outputs a reference voltage to one end of a fifth electric current path from the other end of the fifth electric current path, one end of the fifth electric current path being connected to the other end of the second electric current path of the second transistor; and
a sixth transistor which has a sixth control terminal and resets a voltage applied to the wiring between the second control terminal of the second transistor and the first electric current path of the first transistor by turning on the sixth control terminal by an output signal of the other stage; and
(B) a drive device driven in accordance with the output signal from the second transistor of the shift register,
a value (a channel-width/a channel-length of the fifth transistor) being larger than another value (a channel-width/a channel-length of the first transistor).
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.